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| w WM8224 60msps 3-channel afe with multiple device operation and programmable automatic black level calibration wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/ enews production data, june 2012, rev 4.1 copyright ? 2012 wolfson microelectronics plc. description the WM8224 is an analogue front end/digitiser ic which processes and digitises the analogue output signals from ccd sensors or contact image sensors (cis) at pixel sample rates of up to 60msps. the device includes thr ee analogue signal processing channels each of which contai ns reset level clamping, correlated double sampling and programmable gain and offset adjust functions. the output from each of these channels is time multiplexed into a single high-speed 16-bit analogue to digital converter. t he digital data is available in a variety of output formats via the flexible data port. an internal 4-bit dac is suppli ed for internal reference level generation. this may be used during cds to reference cis signals or during clamping to clamp ccd signals. an external reference level may also be supplied. adc references are generated internally, ensuring optimum performance from the device. a programmable automatic bla ck-level calibration function is available to adjust the dc offset of the output data. a daisy chain feature allows multiple devices to operate together using the same control interface and output data bus. features ? 12 or 16-bit adc, 40msps conversion rate ? 8 or 10-bit adc, 60msps conversion rate ? low power ? 360 mw typical ? 3.3v single supply operation ? 3 channel operation ? daisy chain feature for multiple device use ? correlated double sampling ? programmable gain (9-bit resolution) ? programmable offset adjust (8-bit resolution) ? flexible clamp timing ? programmable clamp voltage ? internally generated voltage references ? automatic black level calibration ? 32-lead qfn package ? serial control interface applications ? digital copiers ? usb2.0 compatible scanners ? multi-function peripherals ? high-speed ccd/cis sensor interface block diagram
WM8224 production data w pd, rev 4.1, june 2012 2 table of contents descript ion ....................................................................................................... 1 ? featur es ............................................................................................................ 1 ? applications ..................................................................................................... 1 ? block diag ram ................................................................................................ 1 ? table of co ntents ......................................................................................... 2 ? pin config uration .......................................................................................... 4 ? ordering info rmation .................................................................................. 4 ? pin descri ption ................................................................................................ 5 ? absolute maximu m ratings ........................................................................ 6 ? recommended operatin g condit ions ..................................................... 6 ? thermal perfo rmance ................................................................................. 6 ? electrical charact eristics ..................................................................... 7 ? 40mhz oper ation ....................................................................................................... 7 ? 60mhz oper ation ....................................................................................................... 7 ? general characteristics ..................................................................................... 9 ? input video sampling ............................................................................................ 11 ? cds mode ( cds=1) .................................................................................................... 11 ? non-cds mode (cds=0) ........................................................................................... 12 ? output data timing ................................................................................................ 14 ? serial interface ..................................................................................................... 15 ? internal power on reset ci rcuit .......................................................... 16 ? device des cription ...................................................................................... 18 ? introduction ........................................................................................................... 18 ? configurable resolution of adc .................................................................... 18 ? input sampling ........................................................................................................ 18 ? reset level clamping (rlc) ................................................................................ 19 ? cds/non-cds processing..................................................................................... 21 ? offset adjust and programmable gain ........................................................ 21 ? adc input black level adjust ........................................................................... 22 ? overall signal flow summary ......................................................................... 23 ? calculating the output co de for a given input ...................................... 24 ? output formats ..................................................................................................... 25 ? programmable automatic blac k level calibration ................................ 26 ? indicating the start of a blc procedure .................................................... 27 ? blc duration control ......................................................................................... 28 ? blc worked example: ............................................................................................ 29 ? blc scenarios of operation.............................................................................. 31 ? references .............................................................................................................. 35 ? power management .............................................................................................. 35 ? control interface ................................................................................................ 35 ? multiple device operation ................................................................................. 36 ? operating modes ................................................................................................... 39 ? 16-bit mode ................................................................................................................ 39 ? 10-bit mode ................................................................................................................ 40 ? device conf iguration ................................................................................. 41 ? register map ............................................................................................................ 41 ? register map d escription .................................................................................. 42 ? applications in formation ........................................................................ 47 ? recommended external components ........................................................... 47 ? recommended external co mponent values .............................................. 47 ? package dime nsions .................................................................................... 48 ? WM8224 production data w pd, rev 4.1, june 2012 3 important no tice ......................................................................................... 49 ? address: .................................................................................................................... 4 9 ? revision hi story ........................................................................................... 50 ? WM8224 production data w pd, rev 4.1, june 2012 4 pin configuration ordering information device temperature range package moisture sensitivity level peak soldering temperature WM8224csefl 0 to 70 o c 32-lead qfn (5x5x0.9mm) (pb-free) msl1 260 ? c WM8224csefl/r 0 to 70 o c 32-lead qfn (5x5x0.9mm) (pb-free, tape and reel) msl1 260 ? c note: reel quantity = 3,500 WM8224 production data w pd, rev 4.1, june 2012 5 pin description pin name type description 1 rsmp digital input reset sample pulse (when cds=1) or clamp control. 2 mclk digital input master (adc) clock. this clock determines the adc conversion rate. 3 dgnd supply digital ground. 4 sen digital input enables the serial interface when high. 5 dvdd supply digital supply for logic, clock gener ator and digital input/output pads. 6 sdi digital input serial interface data input. 7 sck digital input serial interface clock. digital output data bus. adc output data (d15: d0) is available in a variety of output formats. 8 op[0] digital output d0 (lsb) 9 op[1] digital output d1 10 op[2] digital output d2 11 op[3] digital output d3 12 op[4] digital output d4 13 op[5] digital output d5 14 op[6] digital output d6 15 op[7] digital output d7 16 op[8] digital output d8 17 op[9] digital output d9 18 op[10] digital output d10 19 op[11]/sdo digital output d11 (msb) alternatively, pin op[11]/sdo may be us ed to output register read-back data. see serial interface description in device description section for further details. 20 avdd supply analogue supply. this must be operated at the same potential as dvdd. 21 agnd1 supply analogue ground. 22 vrb analogue output lower reference voltage. this pin must be connected to agnd via a decoupling capacitor. 23 vrt analogue output upper reference voltage. this pin must be connected to agnd via a decoupling capacitor. 24 vrx analogue output input return bias voltage. this pin must be connected to agnd via a decoupling capacitor. 25 vrlc/vbias analogue i/o selectable analogue output voltage for rl c or single-ended bias reference. this pin would typically be connect ed to agnd via a decoupling capacitor. vrlc can be externally dr iven if programmed hi-z. 26 binp analogue input blue channel input video. 27 ginp analogue input green channel input video. 28 rinp analogue input red channel input video. 29 agnd2 supply analogue ground. 30 dslct digital tristate input sets 2-bit device id fo r daisy chain operation: 0 = device id is 00 1 = device id is 01 z = device id is 10 31 oeb digital input output hi-z control. all digital output s set to high-impedance state when input pin oeb=1, if autoz=0. note that readback function will override high-impedance on op11 this pin has an internal 100k ? pull-down resistor to agnd. 32 vsmp digital input video sample pulse. WM8224 production data w pd, rev 4.1, june 2012 6 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent damage to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guaranteed performance specificati ons are given under electrical characteristics at the te st conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std- 020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specif ied in ordering information. condition min max analogue supply voltage: avdd gnd - 0.3v gnd + 5v digital supply voltage: dvdd gnd - 0.3v gnd + 5v digital ground: dgnd gnd - 0.3v gnd + 0.3v analogue grounds: agnd1 ? 2 gnd - 0.3v gnd + 0.3v analogue inputs (rinp, ginp, binp) gnd - 0.3v avdd + 0.3v other analogue pins gnd - 0.3v avdd + 0.3v digital i/o pins gnd ? 0.3v dvdd + 0.3v operating temperature range: t a 0 ? c +70 ? c storage temperature prior to soldering 30 ? c max / 85% rh max storage temperature after soldering -65 ? c +150 ? c notes: 1. gnd denotes the voltage of any ground pin. 2. agnd1, agnd2 and dgnd pins are intended to be operat ed at the same potential. differential voltages between these pins will degrade performance. recommended operating conditions condition symbol min typ max units operating temperature range t a 0 70 ? c analogue supply voltage avdd 2.97 3.3 3.63 v digital core and i/o supply voltage dvdd 2.97 3.3 3.63 v thermal performance parameter symbol test conditions min typ max unit performance thermal resistance ? junction to case r jc t ambient = 25c 10.27 c/w thermal resistance ? junction to ambient r ja 29.45 c/w notes: figure 3 figures given are for package mounted on 4-layer fr4 according to jesd51-5 and jesd51-7. WM8224 production data w pd, rev 4.1, june 2012 7 electrical characteristics 40mhz operation test conditions avdd = dvdd = 3.3v, agnd = dgnd = 0v, t a = 25 ? c, mclk = 40mhz unless otherwise stated. parameter symbol test conditions min typ max unit overall system specification (including 16-bit adc, pga, offset and cds functions) max conversion rate 40 msps full-scale input voltage range (see note 1) lowrefs=0, max gain lowrefs=0, min gain 0.25 3.03 vp-p vp-p lowrefs=1, max gain lowrefs=1, min gain 0.15 1.82 vp-p vp-p input signal limits (see note 2) v in fol_en=0 agnd-0.3 avdd+0.3 v fol_en=1, minimum agnd v fol_en=1, maximum agnd+1.2 v input capacitance c in rinp, ginp, binp to agnd 10 pf full-scale transition error gain = 0db; pga[8:0] = 18(hex) 20 mv zero-scale transition error gain = 0db; pga[8:0] = 18(hex) 20 mv differential non-linearity dnl 16-bit 1.2 lsb integral non-linearity (pk-pk/2) inl 16-bit 56 lsb channel to channel gain matching 1.3 % output noise unity gain (unused channels grounded) 10.2 lsb rms programmable gain amplifier resolution 9 bits gain ] : [ pga * . . 0 8 511 34 7 66 0 ? v/v max gain, each channel g max 8 v/v min gain, each channel g min 0.66 v/v analogue to digital converter resolution 16 bits speed 40 msps full-scale input range (2*(vrt-vrb)) lowrefs=0 2 v lowrefs=1 1.2 v 60mhz operation test conditions avdd = dvdd = 3.3v, agnd = dgnd = 0v, t a = 25 ? c, mclk = 60mhz unless otherwise stated. parameter symbol test conditions min typ max unit overall system specification (including 10-bit adc, pga, offset and cds functions) max conversion rate 60 msps full-scale input voltage range (see note 1) lowrefs=0, max gain lowrefs=0, min gain 0.26 3.03 vp-p vp-p lowrefs=1, max gain lowrefs=1, min gain 0.16 1.82 vp-p vp-p input signal limits (see note 2) v in fol_en=0 agnd-0.3 avdd+0.3 v fol_en=1, minimum agnd v fol_en=1, maximum agnd+1.2 v input capacitance c in rinp, ginp, binp to agnd 10 pf full-scale transition error gain = 0db; pga[8:0] = 18(hex) 20 mv WM8224 production data w pd, rev 4.1, june 2012 8 test conditions avdd = dvdd = 3.3v, agnd = dgnd = 0v, t a = 25 ? c, mclk = 60mhz unless otherwise stated. parameter symbol test conditions min typ max unit zero-scale transition error gain = 0db; pga[8:0] = 18(hex) 20 mv differential non-linearity dnl 10-bit 0.5 lsb integral non-linearity (pk-pk/2) inl 10-bit 7 lsb channel to channel gain matching 2.5 % output noise unity gain 10-bit (unused channels grounded) 0.5 lsb rms programmable gain amplifier resolution 9 bits gain ] : [ pga * . . 0 8 511 34 7 66 0 ? v/v max gain, each channel g max 7.7 v/v min gain, each channel g min 0.65 v/v analogue to digital converter resolution 10 bits speed 60 msps full-scale input range (2*(vrt-vrb)) lowrefs=0 2 v lowrefs=1 1.2 v notes: 1. full-scale input voltage denotes the differential input signal amplitude (v in -vrlc in non-cds mode, v in -reset level in cds mode) that can be gained to match the adc full-scale input range. 2. input signal limits are the limits within which each input voltage and vrlc reference must lie. WM8224 production data w pd, rev 4.1, june 2012 9 general characteristics test conditions avdd = dvdd = 3.3v, agnd = dgnd = 0v, t a = 25 ? c parameter symbol test conditions min typ max unit references upper reference voltage vrt lowrefs=0 lowrefs=1 2.05 1.85 v v lower reference voltage vrb lowrefs=0 lowrefs=1 1.05 1.25 v v input return bias voltage vrx 1.25 v diff. reference voltage (vrt- vrb) v rtb lowrefs=0 lowrefs=1 1.0 0.6 v v output resistance vrt, vrb, vrx 1 ?? vrlc/reset-level clamp (rlc) rlc switching impedance 50 ?? vrlc short-circuit current 2 ma vrlc output resistance 2 ? vrlc hi-z leakage current vrlc = 0 to avdd 1 ? a rlcdac resolution 4 bits rlcdac step size v rlcstep rlcdacrng=0, 0.173 v/step v rlcstep rlcdacrng=1, lowrefs=0 0.11 v/step v rlcstep rlcdacrng=1, lowrefs=1 0.097 v/step rlcdac output voltage at code 0(hex) v rlcbot rlcdacrng=0, rlcdac[3:0]=0000, 0.4 v v rlcbot rlcdacrng=1, rlcdac[3:0]=0000, 0.4 v rlcdac output voltage at code f(hex) v rlctop rlcdacrng=0, rlcdac[3:0]=1111, 3.0 v v rlctop rlcdacrng=1, rlcdac[3:0]=1111, lowrefs = 0 2.05 v v rlctop rlcdacrng=1, rlcdac[3:0]=1111, lowrefs = 1 1.85 v vrlc dnl -0.5 +0.5 lsb vrlc inl -0.5 +0.5 lsb offset dac, monotonicity guaranteed resolution 8 bits differential non-linearity dnl 0.1 0.5 lsb integral non-linearity inl 0.75 1 lsb step size 2.04 mv/step output voltage code 00(hex) code ff(hex) -250 +250 mv mv digital specifications digital inputs high level input voltage v ih 0.7 ? dvdd v low level input voltage v il 0.2 ? dvdd v high level input current i ih 1 ? a low level input current i il 1 ? a input capacitance c i 5 pf WM8224 production data w pd, rev 4.1, june 2012 10 test conditions avdd = dvdd = 3.3v, agnd = dgnd = 0v, t a = 25 ? c parameter symbol test conditions min typ max unit digital outputs high level output voltage v oh i oh = 1ma dvdd ? 0.5 v low level output voltage v ol i ol = 1ma 0.5 v high impedance output current i oz 1 ? a digital io pins applied high level input voltage v ih 0.7 ? dvdd v applied low level input voltage v il 0.2 ? dvdd v high level output voltage v oh i oh = 1ma dvdd ? 0.5 v low level output voltage v ol i ol = 1ma 0.5 v low level input current i il 1 ? a high level input current i ih 1 ? a input capacitance c i 5 pf output impedance ro io = 1ma 38 ? high impedance output current i oz 1 ? a supply currents ? analogue supply current ? active fol_en=0 93 ma ? fol_en=1 141 ma ? digital supply current ? active fol_en=0 7.3 ma fol_en=1 8 ma total supply current ? active fol_en=0 100.3 ma fol_en=1 149 ma total supply current ? full power down mode 150 200 ? a WM8224 production data w pd, rev 4.1, june 2012 11 input video sampling cds mode (cds=1) figure 1 three-channel cds operation (cds=1) figure 2 two-channel cds operation (cds=1) WM8224 production data w pd, rev 4.1, june 2012 12 figure 3 one-channel cds operation (cds=1) notes: 1. the relationship between input video signal and sample points is controlled by vsmp and rsmp. 2. when vsmp is high the input video signal is connected to the video sampling capacitors. 3. when rsmp is high the input video signal is connected to the reset sampling capacitors. 4. non-cds operation is also possible; vsmp, mclk timing is unchanged, rsmp is not required in this mode but can be used to control input clamping. non-cds mode (cds=0) figure 4 three-channel non-cds operation (cds=0) WM8224 production data w pd, rev 4.1, june 2012 13 figure 5 two-channel non-cds operation (cds=0) figure 6 one-channel non-cds operation (cds=0) notes: 1. the relationship between input video signal and sample points is controlled by vsmp and rsmp. 2. when vsmp is high the input video si gnal is connected to the video sampling capacitors and vrlc is connected to the reset sampling capacitors. 3. rsmp is not required in this mode but can be used to control input clamping. WM8224 production data w pd, rev 4.1, june 2012 14 test conditions avdd = dvdd = 3.3v, agnd = dgnd = 0v, t a = 25 ? c. parameter symbol test conditions min typ max units mclk period, aclkdiv=00 (default) t per 12 or 16 bit 25 ns t per 8 or 10 bit 16.67 ns mclk high period t mclkh 0.5 mclk periods mclk low period t mclkl 0.5 mclk periods mclk duty cycle 45:55 55:45 % rsmp pulse high time t rsd 3 ns vsmp pulse high time t vsd 2 ns rsmp falling to vsmp rising time t rsfvsr 0 ns mclk rising to vsmp rising time t mrvsr 3 ns mclk falling to vsmp falling time t mfvsf 7 ns vsmp falling to mclk rising time t vsfmr 0 ns 1 st mclk falling edge after vsmp falling to rsmp falling time t mf1rsf 7 ns 3-channel mode pixel period t pr3 3 mclk periods 2-channel mode pixel period t pr2 2 mclk periods 1-channel mode pixel period t pr1 1 mclk periods output latency. from 1 st rising edge of mclk after vsmp falling to data output lat opdel[3:0]=0000, aclkdiv=00 7 mclk periods notes: 1. parameters are measured at 50% of the rising/falling edge. output data timing oeb op hi-z t pze hi-z t pez figure 7 output enable/disable timing from oeb pin mclk op hi-z t pd t paez hi-z t paze figure 8 output enable/disable timing with autoz=1 WM8224 production data w pd, rev 4.1, june 2012 15 test conditions avdd = dvdd = 3.3v, agnd = dgnd = 0v, t a = 25 ? c, mclk = 40mhz unless otherwise stated.. parameter symbol test conditions min typ max units output propagation delay t pd i oh & i ol = 1ma autoz=0 3 4.5 7 ns output enable time, from oeb falling edge t pze 5 ns output disable time, from oeb rising edge. t pez 3 ns automatic output enable time from mclk rising edge. t paze autoz=1, oedel=01 5.5 ns automatic output disable time from mclk rising edge. t paez autoz=1, all oedel settings 3 ns serial interface figure 9 serial interface timing test conditions avdd = dvdd = 3.3v, agnd = dgnd = 0v, t a = 25 ? c, unless otherwise stated. parameter symbol test conditions min typ max units sck period t sper 83.3 ns sck high t sckh 37.5 ns sck low t sckl 37.5 ns sdi set-up time t ssu 6 ns sdi hold time t sh 6 ns sck rising to sen rising t scrser 37.5 ns sck falling to sen falling t scfsef 12 ns sen to sck set-up time t sec 12 ns sen pulse width t sew 60 ns sen low to sdo = register data t serd 30 ns sck low to sdo = register data t scrd 30 ns sck low to sdo = adc data t scrdz 30 ns note: figure 3 parameters are measured at 50% of the rising/falling edge WM8224 production data w pd, rev 4.1, june 2012 16 internal power on reset circuit figure 10 internal power on reset circuit schematic the WM8224 includes an internal power-on-reset circ uit, as shown in figure 10, which is used to reset the digital logic into a default state after power up. the por circuit is powered from avdd and monitors dvdd. it asserts porb low if avdd or dvdd is below a minimum threshold. dvdd avdd v pord_on dgnd agnd internal por active lo hi device ready internal por active no power por undefined v pora_off v pora internal porb figure 11 typical power up sequence where avdd is powered before dvdd figure 11 shows a typical power-up sequence w here avdd is powered up first. when avdd rises above the minimum threshold, vpora, there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. now avdd is at full supply level. next dvdd rises to vpord_on and porb is released high and all registers are in their default state and writ es to the control interface may take place. on power down, where avdd falls first, porb is asserted low whenever avdd drops below the minimum threshold vpora_off. figure 12 typical power up sequence where dvdd is powered before avdd WM8224 production data w pd, rev 4.1, june 2012 17 figure 12 shows a typical power-up sequence where dvdd is powered up first. first it is assumed that dvdd is already up to specified operat ing voltage. when avdd goes above the minimum threshold, vpora, there is enough voltage for the circuit to guarantee porb is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. when avdd rises to vpora_on, porb is released high and all register s are in their default state and writes to the control interface may take place. on power down, where dvdd falls first, porb is asserted low whenever dvdd drops below the minimum threshold vpord_off. symbol min typ max unit v pora 0.4 0.6 0.8 v v pora_on 0.9 1.2 1.6 v v pora_off 0.4 0.6 0.8 v v pord_on 0.5 0.7 0.9 v v pord_off 0.4 0.6 0.8 v table 1 typical por operation (typical values, not tested) note: it is recommended that every time power is cycl ed to the WM8224 a software reset is written to the software register to ensure that the contents of the control registers are at their default values before carrying out any other register writes. WM8224 production data w pd, rev 4.1, june 2012 18 device description introduction a block diagram of the device showing the si gnal path is presented on the front page of this datasheet. the WM8224 samples up to three inputs (rinp, ginp and binp) simultaneously. the device then processes the sampled video signal with respect to the video reset level or an internally/externally generated reference level using betw een one and three processing channels. each processing channel consists of an input sa mpling block with optional reset level clamping (rlc) and correlated double sampling (cds), an 8-bit programmable offset dac and a 9-bit programmable gain amplifier (pga). the processing channel outputs are switched alternat ely by a 3:1 multiplexer to the adc input. the adc then converts each result ing analogue signal to a digital word . the digital output from the adc is presented in a variety of possible output fo rmats onto the output bus, op[11:0]. the twelve output pins can be set to a high impedance state using either the oeb control pin or the opd register bit. on-chip control registers determi ne the configuration of the devic e, including the offsets and gains applied to each channel. these registers are programmable via a serial interface. the device has a black-level calib ration function which allows the d.c. offset determined during the optically-black pixels at the beginning of the linear sensor to be removed during the image-pixels. configurable resolution of adc the WM8224 has a configurable adc resolution. the default setting is 16 bits resolution. this can be changed by the user by changing a register setting. the register res[1:0] can be changed to alter the reso lution from 16 bits to either 12, 10 or 8 bits resolution. input sampling the WM8224 can sample and process up to three inputs through one to three processing channels as follows: colour pixel-by-pixel: the three inputs (rinp, ginp and binp) are simultaneously sampled for each pixel and a separate channel processes each i nput. the signals are then multiplexed into the adc, which converts all three inputs within the pixel period. two channel pixel-by-pixel: two input channels (rinp and ginp, rinp and binp, or ginp and binp) are simultaneously sampled for each pixel and a separate channel processes each input. the signals are then multiplexed into the adc, which c onverts both inputs within the pixel period. the unused channel can be changed via the control in terface. the unused channel is powered down when this mode is selected. monochrome: a single chosen input (rinp, ginp, or binp) is sampled, processed by the corresponding channel, and converted by the adc. the choice of input channel can be changed via the control interface. the unused channels ar e powered down when this mode is selected. WM8224 production data w pd, rev 4.1, june 2012 19 reset level clamping (rlc) to ensure that the signal applied to the WM8224 lies within the supply voltage range (0v to avdd) the output signal from a ccd is usually leve l shifted by coupling through a capacitor, c in. the rlc circuit clamps the WM8224 side of this capacitor to a suitable voltage through a cmos switch during the ccd reset period (pixel clamping) or during the bl ack pixels (line clamping). in order for clamping to produce correct results the input voltage dur ing the clamping must be a constant value. note that if the ac coupling capacitor (c in ) is used in non-cds mode (cds =0), then to minimise code drift, line clamping should be us ed and internal input voltage buffers enabled using the fol_en register bit. alternatively, if t he input signal contains a stable refe rence/reset level then pixel clamping should be used, and the voltage buffers need not be enabled. the WM8224 allows the user to control the rlc switch in a variety of ways as illustrated in figure 13. this figure shows a single channel, however all 3 channels are identical, each with its own clamp switch controlled by the common clmp signal. the method of control chosen depends upon the charac teristics of the input video. the rlcen register bit must be set to 1 to enable clamping, otherwise the rlc switch cannot be closed (by default rlcen=1). note that unused inputs should be left floating, or grounded through a decoupling capacitor, if reset level clamping is used. figure 13 rlc clamp control options when an input waveform has a stable reference le vel on every pixel it may be desirable to clamp every pixel during this period. setting clmpctrl=0 means that the rlc switch is closed whenever the rsmp input pin is high, as shown in figure 14. mclk vsmp rsmp rlc switch control "clmp" (rlcen=1,clmpctrl=0) rlc switch closed when rsmp=1 video sample taken on fallling edge of vsmp reset/reference sample taken on fallling edge of rsmp input video signal reference ("black") level video level figure 14 reset level clamp operation (clmpctr l=0), cds operation shown, non-cds also possible WM8224 production data w pd, rev 4.1, june 2012 20 in situations where the input video signal does not have a stable reference level it may be necessary to clamp only during those pixels which have a known state (e.g. the dummy, or ?black? pixels at the start or end of a line on most image sensors). this is known as line-clamping and relies on the input capacitor to hold the dc level between clamp inte rvals. in non-cds mode (cds=0) this can be done directly by controlling the rsmp input pin to go high during the black pixels only. note that internal input voltage buffers should be enabl ed using the fol_en register bit when using this mode of operation. alternatively it is possible to use rsmp to ident ify the black pixels and enable the clamp at the same time as the input is being sampled (i.e. when vsm p is high and rsmp is hi gh). this mode is enabled by setting clmpctrl=1 and the operation is shown in figure 15. mclk vsmp rsmp rlc switch control, "clmp" (rlcen=1,clmpctrl=1) rlc switch closed when rsmp=1 && vsmp=1 (during "black" pixels) video and reference sample taken on fallling e dge of vsmp input video signal unstable reference level dummy or "black" pixel video level figure 15 reset level clamp operation (clmpctrl=1), non-cds mode only rlcen clampctrl outcome use 0 x rlc is not enabled. rlc switch is always open. when input is dc coupled and within supply rails. 1 0 rlc switch is controlled directly from rsmp input pin: rsmp=0: switch is open rmsp=1: switch is closed when asic explicitly provides a reset sample signal and the input video waveform has a suitable reset level. 1 1 vsmp applied as normal, rsmp is used to indicate the location of black pixels rlc switch is controlled by logical combination of rsmp and vsmp: rsmp && vsmp = 1: switch is closed switch is re-opened when: vsmp=0 (non-cds mode) vsmp=0 and rsmp=0 (cds mode) when clamping during the video period of black pixels or there is no stable per-pixel reference level. this method of operation is generally only sensible in non-cds mode. table 2 reset level clamp control summary WM8224 production data w pd, rev 4.1, june 2012 21 cds/non-cds processing for ccd type input signals, containi ng a fixed reference/reset level, the signal may be processed using correlated double sampling (cds), which will remove pixel-by-pixel common mode noise. with cds processing the input waveform is sampled at two different points in time for each pixel, once during the reference/reset level and once during the vi deo level. to sample using cds, register bit cds must be set to 1 (default). this causes the signal reference to come from the video reference level as shown in figure 16. the video sample is always taken on the falli ng edge of the input vsmp signal (vs). in cds-mode the reset level is sampled on the falling edge of the rsmp input signal (rs). for input signals that do not contain a referenc e/reset level (e.g. cis sensor signals), non-cds processing is used (cds=0). in this case, the video level is processed with respect to the voltage on pin vrlc/vbias. the vrlc/vbias voltage is samp led at the same time as vsmp samples the video level in this mode. note that if the ac coupling capacitor (c in ) is used in non-cds mode (cds=0), then to minimise code drift, line clampi ng should be used and internal input voltage buffers enabled using the fol_en register bit. alternativ ely, if the input signal contains a stable reference/reset level then pixel clamping s hould be used, and the voltage buffers need not be enabled. figure 16 cds/non-cds input configuration offset adjust and programmable gain the output from the cds block is a differential si gnal, which is added to the output of an 8-bit offset dac to compensate for offsets and then amplified by a 9-bit pga. the gain and offset for each channel are independently programmable by writing to control bits dac[7:0] and pga[8:0]. the gain characteristic of the WM8224 pga is s hown in figure 17. figure 18 shows the maximum device input voltage that can be gained up to matc h the adc full-scale input range (default=2v). WM8224 production data w pd, rev 4.1, june 2012 22 0 1 2 3 4 5 6 7 8 0 128 256 384 512 gain code (pga[8:0]) pga gain (v/v) 0 0.5 1 1.5 2 2.5 3 3.5 0 128 256 384 512 gain code (pga[8:0]) input voltage range (v) max i/p v oltage lowrefs=0 max i/p v oltage lowrefs=1 figure 17 pga gain characteristic figure 18 peak input voltage to match adc full-scale range adc input black level adjust the output from the pga can be offset to match t he full-scale range of the differential adc (2*[vrt- vrb]). for negative-going input video signals, a black level (z ero differential) output from the pga should be offset to the top of the adc range by setting regist er bits pgafs[1:0]=10. this will give an output code of ffff (hex) from the WM8224 for zero input. if code zero is required for zero differential input then the invop bit should be set. for positive going input signals the black level shoul d be offset to the bottom of the adc range by setting pgafs[1:0]=11. this will give an output code of 0000 (hex) from the WM8224 for zero input. bipolar input video is accommodated by setting pgafs[ 1:0]=00 or pgafs[1:0]=01. zero differential input voltage gives mid-range adc output, 7fff (hex). WM8224 production data w pd, rev 4.1, june 2012 23 figure 19 adc input black level adjust settings overall signal flow summary figure 20 represents the processing of the video signal through the WM8224. v reset v vrlc v 3 cds = 1 cds = 0 cdacpd=1 250mv*(dac[7:0]-127.5)/127.5 analo g - x + + see parametrics for dac voltages. op pins d 1 digita l adc block pga block offset dac block input sampling block d 2 cds, cdacpd,cdac[3:0], dac[7:0], pga[8:0], pgafs[1:0] and invop are set by programming internal control registers. cds=1 for cds, 0 for non-cds v in is rinp or ginp or binp v reset is v in sampled during reset clamp v rlc is voltage applied to vrlc/vbias pin v in x (65535/v fs ) +0 if pgafs[1:0]=11 +65535 if pgafs[1:0]=10 +32768 if pgafs[1:0]=0x pga gain a= 0.66+pga[8:0]x7.34/511 output invert block d2 = d1 if invop = 0 d2 = 65535-d1 if invop = 1 offset dac rlc dac + v 2 v 1 cdacpd=0 figure 20 overall signal flow the input sampling block produces an effective input voltage v 1 . for cds, this is the difference between the input video level v in and the input reset level v reset . for non-cds this is the difference between the input video level v in and the voltage on the vrlc/vbias pin, v vrlc , optionally set via the rlc dac. the offset dac block then adds the amount of fine offset adjustment required to move the black level of the input signal towards 0v, producing v 2 . the pga block then amplifies the white level of the input signal to maximise the adc range, outputting voltage v 3 . the adc block then converts the analogue signal, v 3 , to a 16-bit unsigned digital output, d 1 . the digital output is then inverted, if required, through the output invert block to produce d 2. WM8224 production data w pd, rev 4.1, june 2012 24 calculating the output code for a given input the following equations describe the processi ng of the video and reset level signals through the WM8224. input sampling block: input sampling and referencing if cds = 1, (i.e. cds operation) the previously sampled reset level, v reset , is subtracted from the input video, v in (= rinp, ginp or binp). v 1 = v in ? v reset eqn. 1 if cds = 0, (non-cds operation) the simultaneously sampled voltage on pin vrlc is subtracted instead. v 1 = v in ? v vrlc eqn. 2 if vrlcdacpd = 1, v vrlc is an externally applied voltage on pin vrlc/vbias. if vrlcdacpd = 0, v vrlc is the output from the internal rlc dac. v vrlc = (v rlcstep ? rlc dac[3:0]) + v rlcbot eqn. 3 v rlcstep is the step size of the rlc dac and v rlcbot is the minimum output of the rlc dac. offset dac block: off set (black-level) adjust the resultant signal v 1 is added to the offset dac output. v 2 = v 1 + {250mv ? (dac[7:0]-127.5) } / 127.5 eqn. 4 pga node: gain adjust the signal is then multiplied by the pga gain. v 3 = v 2 ? (0.66 + pga[8 :0]x7.34/511) eqn. 5 adc block : analogue-digital conversion the analogue signal is then convert ed to a 16-bit unsigned number, with input range configured by pgafs[1:0]. d 1 [15:0] = int{ ( v 3 /v fs ) ? 65535} + 32767 pgafs[1:0] = 00 or 01 eqn. 6 d 1 [15:0] = int{ ( v 3 /v fs ) ? 65535} pgafs[1:0] = 11 eqn. 7 d 1 [15:0] = int{ ( v 3 /v fs ) ? 65535} + 65535 pgafs[1:0] = 10 eqn. 8 where the adc full-scale range, v fs = 2v when lowrefs=0 and v fs = 1.2v when lowrefs=1. output invert block: polarity adjust the polarity of the digital output may be inverted by control bit invop. d 2 [15:0] = d 1 [15:0] (invop = 0) eqn. 9 d 2 [15:0] = 65535 ? d 1 [15:0] (invop = 1) eqn. 10 WM8224 production data w pd, rev 4.1, june 2012 25 output formats the output from the WM8224 can be presented in several different formats under control of the opform register bit as shown in figure 21. in addition the data can be presented at different resolutions. figure 21 output data formats opform output format output pins res[1:0] resolution output 0 multiplexed op[11:4] 11 16-bit a[7:0] = {d15, d14, d13, d12, d11, d10, d9, d8} b[7:0] = {d7, d6, d5, d4, d3, d2, d1,d0} 10 12-bit a[7:0] = {d15, d14, d13, d12, d11, d10, d9, d8} b[7:0] = {d7, d6, d5, d4, 0, 0, 0, 0} 01 10-bit a[7:0] = {d15, d14, d13, d12, d11, d10, d9, d8} b[7:0] = {d7, d6, 0, 0, 0, 0, 0, 0} 00 8-bit not valid 1 parallel op[11:0] 11 16-bit not valid op[11:0] 10 12-bit a[11:0] ={ d15, d14, d13, d12, d11, d10, d9, d8,d7,d6,d5,d4} op[11:2] 01 10-bit a[9:0] = {d15, d14, d13, d12, d11, d10, d9, d8,d7,d6} op[11:4] 00 8-bit a[7:0] = {d15, d14, d13, d12, d11, d10, d9, d8} table 3 details of output data formats (as shown in figure 21) WM8224 production data w pd, rev 4.1, june 2012 26 programmable automatic black level calibration the programmable automatic black-level calibration (blc ) function is to adjust the d.c. offset of the output data such that the digital output code for black pi xels is calibrated to a target black level value. the d.c. offset is determined during the optically-b lack pixels at the beginning of the linear sensor, and removed during the image-pixe ls as shown in figure 22 . black pixel period image pixel period determine black level offset remove black level offset from image pixels figure 22 linear sensor model the automatic black level calibration operates a ssuming 12 bits adc resolution. adjustments to calculations must be made fo r different adc resolutions. the black level calibration process occurs in two stages as shown in figure 23 below: ? coarse adjust calibration : this is a mixed signal loop whic h removes the coarse offset by adjusting the offset dac. ? fine adjust calibration: this is a digital loop which removes the remaining offset with better noise tolerance, utilising adc ove r-range to improve the dynamic range of the system. target bl input black level v1 adjusted adc output pga adc offset dac mixed signal loop digits coarse adjust calibration fine adjust calibration digital loop digits figure 23 blc top-level circuitry target codes the user must specify a target black leve l for each red, green and blue channel through the registers targetr, targetg and targetb. if, dur ing the black-pixel period, the average adc output code was, for example, 100 and the user spec ified the target black level code to be 10, the blc circuitry would determine 90 codes should be subtracted from the adc output. these 90 codes will then be subtracted from every image-pixel code output from the adc. note ? changing the pga gain affects the black-le vel through the device; the gain should therefore not be changed during a blc procedure. if the pg a gain changes, then the blc routine should be re-run. the automatic black level calibration feature operates with the assumption of a 12bit adc resolution. the register settings for target codes (targe tx[7:0]) should be set differently depending on the WM8224 production data w pd, rev 4.1, june 2012 27 adc resolution being used. as targetx[7:0] is an 8 bit register, the 4 msbs of a data output code cannot be changed. 16bit adc resolution for 16bit resolution the target code entered into targ etx[7:0] will ignore the 4 msbs and 4 lsbs of the 16-bit data output. for example if t he desired code out is 0000111111110001, the value entered into targetx[7:0] would be 11111111. 12bit adc resolution for 12bit resolution the 4 msbs of the 12 bit data output code will be ignored. for example if the desired code out is 000011111111, the value entered into targetx[7:0] would be 11111111. 10bit adc resolution for 10bit resolution the 4 msbs of the 10bit data output code will be ignored. the 2 lsbs of the target code should be set to ?00?. for exam ple if the desired code out is 0000111111, the value entered into targetx[7:0] would be 11111100. 8bit adc resolution for 8bit resolution the 4 msbs of the 8bit data output code will be ignored. the 4 lsbs of the target code should be set to ?0000?. for example if t he desired code out is 00001111, the value entered into targetx[7:0] would be 11110000. indicating the start of a blc procedure the start of a line is required to be indicated to the WM8224 to allow the black-pixel period to be located. this can be achieved by two methods. t he register tg_method is set to reflect which method is to be used. method 1: oeb pin the oeb pin can be shared with the blc function to i ndicate the start of a line if the oeb functionality is not required. to indicate the start of a line, send a line synchronisation pulse, tg, on the oeb pin. it must be high for at least one rising edge of mclk. the tg_method register must be set to either ?10? or ?11? depending on whether pos itive or negative edge triggering is required, as shown in figure 24. figure 24 start of line indicator using tg on the oeb pin WM8224 production data w pd, rev 4.1, june 2012 28 method 2: register write the start of a line can also be indicated using a r egister write to tg_reg. the first rising edge of mclk after tg_reg goes high will indicate the start of the line. tg_reg shall be automatically set to zero by the device. this process can be repeated to indicate the start of a second line, as shown in figure 25. set tg_method to ?00? figure 25 start of line indicator using tg_reg blc duration control dummy pixel delay once the start of line has been determined there can be a delay to allow for the dummy pixels at the start of the sensor to be ignored. this is controll ed by blc_del, which is the number of pixels there should be between the start of line indicator and the start of the blc routine. the register bpix_avail must also be set up for the num ber of black pixels available to carry out the calibration. the durations of the coarse adjust calibration and fine adjust calibration can then be determined as detailed below. figure 26 blc duration control coarse adjust calibration iteration duration the duration of one iteration of the coarse adjust is an integer number of vsmp periods. the exact number of vsmp periods depends on the mclk:vsm p ratio and the number of channels used. the implementation ensures that there are at least a certain number of mclk?s per coarse adjust iteration as shown in table 4. WM8224 production data w pd, rev 4.1, june 2012 29 mode minimum no. of mclks per coarse adjust iteration 3-channel 11 2-channel 10 mono 9 table 4 modes vs mclks for coarse iterations the blc design rounds the coarse adjust iteration duration up to a whole number of pixels (i.e. the iteration duration will be a whole number of vsmp periods). fine adjust calibration duration the fine adjust calibration duration is determined by the number of remaining black pixels after the coarse adjust has taken place. blc test mode this mode allows the status of the blc to be s een on the 2 lsbs of the output data pins op[1:0]. this mode could be enabled during the setup stage of the device to ensure that the black level calibration does not encroach on the active pixel dat a. set the stateout register to enable this mode. once the blc register values have been deter mined this register shoul d be disabled. table 5 shows the description of the output data. data on op[1:0] description 00 no blc 01 dummy pixels 10 coarse adjust calibration 11 fine adjust calibration table 5 test mode outputs blc worked example: below is an example of how to configur e the WM8224 for black level calibration. assumptions mclk frequency = 40mhz vsmp frequency = 13.33mhz mode of operation = 3 channel mode black pixels on sensor = 50 dummy pixels on sensor = 20 the following stages set up the black level ca libration although not all stages may be required depending on the application: 1. set up the dummy pixel delay 2. define the coarse adjust calibration 3. define the fine adjust calibration WM8224 production data w pd, rev 4.1, june 2012 30 1. dummy pixel delay set blc_del, the number of dummy pixels for the sensor blc_del = ?0010100? the duration for this will then be blc_del * vsmp period dummy pixel delay = 20*75ns = 1.5us 2. define the coarse adjust loop when setting the coarse adjust calibration it is necessary to bear in mind the following: ? the number of black pixels available ? the coarse adjust iteration duration ? the number of iterations required. step 1: set up bpix_avail with the number of available black pixels for the sensor. bpix_avail = ?0000110010? step 2: calculate mclk:vsmp ratio 40:13.33 = 3:1 step 3: calculate the duration of the iteration in no. of pixels (round up value). refer to table 4 for the number of mclk?s per coarse adjust iteration round up this value to give the no of pixels per iteration = 4 pixels per iteration note: the device will automatically calculate this value. step 4: set the register cadur for max number of iterations. cadur = 2 theoretically there can be 7 coarse adjust iterations during the black pixel period. however, in most cases 2 would be sufficient depending on the number of bl ack pixels available to allow time for the fine adjust loop. 3. fine adjust calibration step 1: enable register fa_en to allow for fine adjust calibration step 2: the time available for fine adjustment is determined by the no. of remaining black pixels after the coar se adjust has taken place. bpix_avail ? (cadur* iteration duration) 50 ? (2*4) = 42 pixels pixels of no ratio vsmp mclk mclks of no . ) : ( . ? 67 . 3 3 11 ) : ( . ? ? ratio vsmp mclk mclks of no WM8224 production data w pd, rev 4.1, june 2012 31 blc scenarios of operation the blc can be used in various ways to suit the application, for example calibration can be done once per page or once per line. register set up shoul d be carried out before the start of a frame and is not required to be done on a line by line basis if using the method 1 oeb pin method. five potential scenarios of operation are suggested below. note: the registers frame_start and seq_start when set high by the user will automatically be set low by the device. scenario 1 coarse adjust calibration enabled for the 1 st line, fine adjust calibration enabled every line with the fine adjust calibration result recalculated every line. this scenario is suitable for dealing with large amounts of d.c. drift throughout a frame; but this is at a cost of potential line-by-line variation in the fine adjust result (dependent on sensor noise and t he pga gain). table 6 shows which registers are required for this scenario with example settings. setup register bpix_avail cadur frame_start fa_everyline value 50 2 1 1 table 6 example register settings for scenario 1 figure 27 scenario 1 WM8224 production data w pd, rev 4.1, june 2012 32 scenario 2 coarse adjust and fine adjust calibration enabled for the 1 st line, with the fine adjust result updated on the 1 st line only. this scenario is suitable for adjusti ng for black-level d.c. drift on a frame-by-frame basis; there will be no line-by-line variation in the bl ack-level from the blc circuitry. table 7 shows which registers are required for th is scenario with example settings. setup register bpix_avail cadur frame_start value 50 2 1 table 7 example register settings for scenario 2 figure 28 scenario 2 scenario 3 coarse adjust calibration enabled for the 1 st line, fine adjust calibration enabled every line with the fine adjust result accumulated throughout frame and used every line. this scenario allows any variation in the black-level to be tracked throughout the frame by accumulating the fine adjust result over multiple lines. this method does not deal wi th as large amounts of d.c. drift throughout the frame as scenario 1, but it will produce less line-by- line variation. table 8 shows which registers are required for this scenario with example settings. setup register bpix_avail cadur frame_start fa_everyline fa_accum value 50 2 1 1 1 table 8 example register settings for scenario 3 figure 29 scenario 3 WM8224 production data w pd, rev 4.1, june 2012 33 scenario 4 coarse adjust calibration enabled for 1 st line, fine adjust calibration enabled every line with the fine adjust result accumulated throughout frame and used at start of next frame. this scenario is intended to be used with a sequence of multiple fr ames, the first frame bei ng used as a calibration frame. this is good for use with s ensors containing very few black-pixe ls as the black-level offset can be calculated over an entire frame and there will be no li ne-by-line variation in the black-level from the blc circuitry. table 9 shows which registers are required for this scenario with example settings. setup register bpix_avail cadur frame_start frame_seq seq_start fa_ everyline fa_a ccum value 50 2 1 1 1 1 1 table 9 example register settings for scenario 4 figure 30 scenario 4 WM8224 production data w pd, rev 4.1, june 2012 34 scenario 5 this scenario utilises the information from a possible calibration black-strip at the start of a scan. the register line_del sets the number of lines from t he start of the frame that the blc procedure is to be performed, so as to coincide with the calibration strip. table 10 shows which registers are required for this scenario with example settings. setup register bpix_avail cadur line_del frame_start fa_everyline value 1000 2 50 1 1 table 10 example register settings for scenario 5 figure 31 scenario 5 WM8224 production data w pd, rev 4.1, june 2012 35 references the adc reference voltages are derived from an internal bandgap reference, and buffered to pins vrt and vrb, where they must be decoupled to ground. pin vrx is driven by a similar buffer, and also requires decoupling. the output buffer from the rlcdac also requires decoupling at pin vrlc/vbias. the adc references can be switched from the def ault values (vrt=2.05v, vrb=1.05v, adc input range=2v) to give a smaller adc reference r ange (vrt=1.85v, vrb=1.25v, adc input range=1.2v) under control of the lowrefs register bit. setti ng lowrefs=1 allows smaller input signals to be accommodated. note: when lowrefs = 1 the output of the rlcdac will scale if rlcdacrng = 1. the max output from rlcdac will change from 2.05 to 1.85v and the step size will proportionally reduce. power management power management for the device is performed via the c ontrol interface. by default the device is fully enabled. the en bit allows the device to be fully powered down when set low. individual blocks can be powered down using the bits in setup regist er 5. when in mono or twochan mode the unused input channels are automatically di sabled to reduce power consumption. note: it is recommended that if the clocks are removed from the devic e, the device should be powered down using the en bit in setup reg 1. control interface the internal control registers are programmable via the serial digital control interface. the register contents can be read back via the serial interface on pin op[11]/sdo. it is recommended that a software reset is carried out after the power-up sequence, before writing to any other register. this ensures that all register s are set to their default values (as shown in table 15). device identification up to 3 WM8224 devices can share a common set of serial interface pins. each device on the common interface bus must be given a different devic e id. the device id is set by the input pin dslct as shown in table 11. dslct device id (id[1:0]) 0 00 1 01 z 10 table 11 device identification register write figure 32 shows sequence of operations for performing a register write. three pins, sck, sdi and sen are used for the control interface. an eight-bit address (id1, id0, a5, 0, a3, a2, a1, a0) is clocked in through sdi, msb first, followed by an eight-bit data word (b7, b6, b5, b4, b3, b2, b1, b0), also msb first. the device id bits indicate which device is being written to on a shared control bus. a register write with device id set to 11 writes data to a ll devices on the common bus. setting address bit a4 to 0 indicates that the operation is a register write. each bit is latched on the rising edge of sck. when the data has been shifted into the device, a risi ng edge on the sen pin transfers the data to the appropriate internal register. WM8224 production data w pd, rev 4.1, june 2012 36 figure 32 control interface register write a software reset is carried out by writing to address ?000100? with any value of data, (i.e. data word = xxxxxxxx). register read-back figure 33 shows register read-back in serial mode. r ead-back is initiated by writing to the serial bus as described above but with address bit a4 set to 1, followed by an 8-bit dummy data word. writing address (id1, id0, a5, 1, a3, a2, a1, a0) will cause the contents (d7, d6, d5, d4, d3, d2, d1, d0) of corresponding register in the addressed device to be output msb first on pin sdo (on the falling edge of sck). note that pin sdo is shared with an output pin, op[11], and readback will override a high- impedance output on this pin. the next word may be read in to sdi while the previous word is still being output on sdo. figure 33 serial interface register read-back multiple device operation up to 3 WM8224 devices can be configured to s hare common serial interfaces and output data buses. in order to accommodate multiple devices on a shared output bus a higher number of mclks per vsmp are required. when multiple devices are being used the WM8224 c an be configured so that the outputs are high impedance apart from during valid data output by setting the autoz register bit to 1. [note that autoz should not be used if the mclk : vsmp ra tio is 1:1.] the output of each device can be staggered by adjusting the latency via the opdel[3:0] r egister bits, allowing multiple devices to share the same output bus. bus contention in 3 channel mode, an mclk:vsmp ratio of 8:1 (2 devices) or 12:1 (3 dev ices) is recommended to give an spare mclk cycle in which to allow the output data pins to transition in and out of a high impedance state. however an mclk:vsmp ratio of 6: 1 (2 devices) or 9:1 (3 devices) can be used, but care must be taken with output timing to prevent bus contention. WM8224 production data w pd, rev 4.1, june 2012 37 example : two device, 6-channel, mclk:vsmp=8:1, operation figure 34 shows how two devices can be configured to share a si ngle data bus and a single control interface bus thus reducing pi n count on the receiving asic. the timing for this mode is shown in figure 35. multi channel sensor figure 34 two device, 6-channel, mclk:vsmp=8:1, schematic figure 35 two device, 6-channel, mclk:vsmp=8:1, timing diagram operating multiple devices at up to 60mhz in up to 16 bit mode if using multiple devices, then up to 16bit operati on can be obtained with an mclk frequency of up to 60mhz, by dividing down the inte rnal mclk, using aclkdiv. WM8224 production data w pd, rev 4.1, june 2012 38 figure 36 timing with aclk=mclk/2 (aclkdiv=01) figure 37 timing with aclk=mclk/3 (aclkdiv=10) figure 38 invalid rsmp positions WM8224 production data w pd, rev 4.1, june 2012 39 operating modes table 12 and table 13 below show the normal operati ng modes of the device. the mclk speed can be changed along with the mclk:vsmp ratio to achieve the desired sample rate. 16-bit mode number of channels description cds available maximum sample rate timing requirements register settings 9 3 devices used yes 4.4 msps mclk max = 40mhz minimum mclk:vsmp ratio = 9:1 mono = 0 twochan = 0 autoz=1 aclkdiv = 00 dev id opdel[3:0] 00 0000 01 0100 10 1000 6 2 devices used yes 6.6 msps mclk max = 40mhz minimum mclk:vsmp ratio = 6:1 mono = 0 twochan = 0 autoz=1 aclkdiv = 00 dev id opdel[3:0] 00 0000 01 0100 9 3 devices used yes 6.6 msps mclk max = 60mhz minimum mclk:vsmp ratio = 9:1 mono = 0 twochan = 0 autoz=1 aclkdiv = 10 dev id opdel[3:0] 00 0000 01 0100 10 1000 6 2 devices used yes 10 msps mclk max = 60mhz minimum mclk:vsmp ratio = 6:1 mono = 0 twochan = 0 autoz=1 aclkdiv = 01 dev id opdel[3:0] 00 0000 01 0100 3 three channel pixel-by-pixel yes 13.33 msps mclk max = 40mhz minimum mclk:vsmp ratio = 3:1 mono = 0 twochan = 0 2 two channel pixel-by-pixel yes 20 msps mclk max = 40mhz minimum mclk:vsmp ratio = 2:1 mono = 0 twochan = 1 1 one channel pixel-by-pixel yes 40 msps mclk max = 40mhz minimum mclk:vsmp ratio = 1:1 mono = 1 twochan = 0 table 12 WM8224 16-bit normal operating modes WM8224 production data w pd, rev 4.1, june 2012 40 10-bit mode number of channels description cds available maximum sample rate timing requirements register settings 9 3 devices used yes 6.6 msps mclk max = 60mhz minimum mclk:vsmp ratio = 9:1 mono = 0 twochan = 0 autoz=1 dev id opdel[3:0] 00 0000 01 0100 10 1000 6 2 devices used yes 10 msps mclk max = 60mhz minimum mclk:vsmp ratio = 6:1 mono = 0 twochan = 0 autoz=1 dev id opdel[3:0] 00 0000 01 0100 3 three channel pixel-by-pixel yes 20 msps mclk max = 60mhz minimum mclk:vsmp ratio = 3:1 mono = 0 twochan = 0 2 two channel pixel-by-pixel yes 30 msps mclk max = 60mhz minimum mclk:vsmp ratio = 2:1 mono = 0 twochan = 1 1 one channel pixel-by-pixel yes 60 msps mclk max = 60mhz minimum mclk:vsmp ratio = 1:1 mono = 1 twochan = 0 table 13 WM8224 10-bit normal operating modes table 14 below shows the different channel mode regi ster settings required to operate the 8224 in 1, 2 and 3 channel modes. mono twochan chan[1:0] mode description 0 0 xx 3-channel (colour mode) 0 1 00 2-channel mode green and blue channels selected, red pga disabled 0 1 01 2-channel mode red and blue channels selected, green pga disabled 0 1 10 2-channel mode red & green channels selected, blue pga disabled 1 0 00 1-channel (monochrome) mode. red channel selected, green and blue pgas disabled. 1 0 01 1-channel (monochrome) mode. green channel selected, red and blue pgas disabled. 1 0 10 1-channel (monochrome) mode. blue channel selected, red and green pgas disabled. x x 11 invalid mode 1 1 xx invalid mode table 14 sampling mode summary note : unused input pins should be connected to agnd unless reset level clamping is used. WM8224 production data w pd, rev 4.1, june 2012 41 device configuration register map the following table describes the location of each control bit used to determine the operation of the WM8224. addres s WM8224 production data w pd, rev 4.1, june 2012 42 register map description the following table describes the function of eac h of the control bits shown in table 15. register register name bit no bit name(s) default description r0 (00h) device id 7:0 10000010 read only register. reading from this register returns the first 2 digits of device part number. r1 (01h) setup register 1 0 en 1 global enable 0 = complete power down, 1 = fully active (individual blocks can be disabled using individual powerdown bits ? see setup register 5). 1 cds 1 select correlated double sampling mode: 0 = non-cds mode, 1 = cds mode. 2 mono 0 sampling mode select 0 = other mode (2 or 3-channel) 1 = monochrome (1-channel) mode. input channel selected by chan[1:0] regi ster bits, unused channel is powered down. twochan and mono should not be set concurrently. 3 twochan 0 sampling mode select 0 = other mode (1 or 3-channel) 1 = 2-channel mode. twochan and mono should not be set concurrently. 5:4 pgafs[1:0] 00 offsets pga output to optimise the adc range for different polarity sensor output signals. zero differential pga input signal gives: 0x = zero output from the pga (output code=511) 10 = full-scale positive output (op=1023) ? use for negative going video. nb, set invop=1 if zero differential input should give a zero output code with negative going video. 11 = full-scale negative output (op=0) - use for positive going video 7:6 aclkdiv[1:0] 00 reduces the internal clock frequency to allow analogue circuitry to run at a slow er rate when daisy chaining devices. 00 ? no divide 01 ? divide mclk by 2 internally 10 ? divide mclk by 3 internally 11 ? not valid WM8224 production data w pd, rev 4.1, june 2012 43 register register name bit no bit name(s) default description r2 (02h) setup register 2 0 opform 0 output format : 0 = multiplexed mode 1 = parallel mode 1 autoz 0 when set the output goes to high impedance other than during valid data output. this will override the oeb/opd control. 0 = output pins high impedance mode controlled by opd/oeb 1 = output pins high impedance mode controlled automatically. normally used in multiple device mode where several devices share a common data bus. autoz should not be set if mclk:vsmp is 1:1. 2 invop 0 digitally inverts the polarity of output data. 0 = negative going video gives negative going output, 1 = negative-going video gives positive going output data. 3 opd 1 output disable. this works with the oeb pin to control the output pins. this is only valid if autoz=0. 0=digital outputs enabled, 1=digital outputs high impedance oeb (pin) opd op pins 0 0 enabled 0 1 high impedance 1 0 high impedance 1 1 high impedance 4 lowrefs 0 reduces the adc reference range (2*[vrt-vrb]), thus changing the max/min input video voltages (adc ref range/pga gain). 0= adc reference range = 2.0v 1= adc reference range = 1.2v 5 rlcdacrng 1 sets the output range of the rlcdac. 0 = rlcdac ranges from 0 to avdd (approximately), 1 = rlcdac ranges from 0 to vrt (approximately). 7:6 res[1:0] 11 controls the device output resolution: res output resolution 00 8-bit 01 10-bit 10 12-bit 11 16-bit r3 (03h) setup register 3 3:0 rlcdac[3:0] 1111 controls rlcdac driving vrlc/vbias pin to define single ended signal reference voltage or reset level clamp voltage. see electrical characteristics section for ranges. 5:4 oedel[1:0] 01 adjustable delay for beginning of automatic oe signal. only valid when autoz=1 00 : typically adds 0.5ns to t pd time 01 : typically adds 1.0ns to t pd time 10 : typically adds 1.5ns to t pd time 11 : typically adds 2.0ns to t pd time 7:6 chan[1:0] 00 when mono=0 and twochan=0 th is register bit has no effect when mono=1: 00 = red channel select 01 = green channel select 10 = blue channel select 11 = reserved WM8224 production data w pd, rev 4.1, june 2012 44 register register name bit no bit name(s) default description when twochan=1: 00 = red pga disabled (g&b only) 01 = green pga disabled (r&b only) 10 = blue pga disabled (r&g only) 11 = reserved r4 (04h) software reset 7:0 00100100 any write to software reset causes all register bits to be reset. it is recommended that a software reset be performed after a power-up before any other register writes. reading from this register returns the last 2 digits of the device part number. r5 (05h) device id revision 7:0 00000001 reading from this register returns the revision number of the device. r6 (06h) setup register 4 3:0 reserved 0000 must be set to 0000 7:4 opdel[3:0] 000 output latency adjust (aclkdiv=00). 0000 = minimum latency (7 mclk periods) 0001 = 8 mclk periods 0010 = 9 mclk periods 0011 = 10 mclk periods 0100 = 11 mclk periods 0101 = 12 mclk periods 0110 = 13 mclk periods 0111 = 14 mclk periods 1000 = 15 mclk periods 1001 to 1111 = invalid settings r7 (07h) setup register 5 0 redpd 0 when set powers down red s/h, pga 1 grnpd 0 when set powers down green s/h, pga 2 blupd 0 when set powers down blue s/h, pga 3 adcpd 0 when set powers down adc. allows reduced power consumption without powering down the references which have a long time constant when switching on/off due to the external decoupling capacitors. 4 vrlcdacpd 0 when set powers down 4-bit rlcdac, setting the output to a high impedance state and allowing an external reference to be driven in on the vrlc/vbias pin. 5 adcrefpd 0 when set disables vrt, vrb buffers to allow external references to be used. 7:6 reserved 00 must be set to 00 r8 (08h) setup register 6 4:0 reserved 00000 must be set to 0 5 rlcen 1 reset level clamp enable. when set reset level clamping is enabled. the method of clamping is determined by clampctrl. 6 clampctrl 0 0 = rlc switch is controlled directly from rsmp input pin: rsmp = 0: switch is open rmsp = 1: switch is closed 1 = rlc switch is controlled by logical combination of rsmp and vsmp. rsmp && vsmp = 0: switch is open switch is re-opened when: vsmp=0 (non-cds mode) vsmp=0 and rsmp=0 (cds mode) 7 fol_en 0 enables internal input volt age buffers, to minimise code drift if not pixel clamping, when using an ac coupling capacitor in non-cds mode (cds=0). line clamping should be used when this bit is set. WM8224 production data w pd, rev 4.1, june 2012 45 register register name bit no bit name(s) default description r9 (09h) blc red target 7:0 targetr [7:0] 00000000 target black-level code for red channel. please see the target codes section for details. r10 (0ah) blc green target 7:0 targetg [7:0] 00000000 target black-level code for green channel. please see the target codes section for details. r11 (0bh) blc blue target 7:2 targetb [7:0] 00000000 target black-level code for blue channel. please see the target codes section for details. r12 (0ch) blc control 1 1:0 tg_method [1:0] 00 determines the start-of-line method to be used. 00 = tg_reg method 01 = not a valid option 10 = oeb/tg shared pin method, +ve edge triggered 11 = oeb/tg shared pin method, -ve edge triggered 2 tg_reg 0 register flag to indicate a star t-of-line, this register is automatically set to zero after it has been clocked by the blc. 3 fscale_ rel 0 inverts the black-level target c odes so they are relative to fullscale. 4 reserved 0 set to zero 6:5 reserved 00 set to zero 7 state_out 0 outputs the 2-bit state of the blc onto op0 and op1. r13 (0dh) blc control 2 2:0 cadur[2:0] 000 controls the number of coarse adjust iterations to be performed. 3 fa_en 0 enables the fine adjust operation 7:4 reserved 0000 set to zero r14 (0eh) blc control 3 0 frame_ start 0 register to indicate that the next start-of-line indicator is the first line in a frame. this register is automatically set to zero at the end of the blc operation on the first line. 1 seq_start 0 register to indicate that the next start-of-line indicator is the first line of the first fram e in a frame-sequence. this register is automatically set to zero at the end of the blc operation on the first line. 2 frame_seq 0 indicates that the blc is to be used in a sequence of frames 3 fa_accum 0 makes the fine adjust calibration accumulate a result over multiple lines. 4 fa_ everyline 0 0 = fine adjust only used on the 1 st line of a frame 1 = fine adjust used on every line of a frame 5 ca_ everyline 0 0 = coarse adjust only used on the 1 st line of a frame 1 = coarse adjust used on every line of a frame 7:6 bpix_avail [9:8] 00 msbs of the number of black- pixels available over which to perform the coarse and/or fine adjust calibration. r15 (0fh) blc control 4 7:0 bpix_avail [7:0] 00000000 lsbs of the number of black-pi xels available over which to perform the coarse and/or fine adjust calibration. r32 (20h) offset dac (red) 7:0 dacr[7:0] 10000000 red channel 8-bit offset dac value (mv) = 250*(dacr[7:0]-127.5)/127.5 r33 (21h) offset dac (green) 7:0 dacg[7:0] 10000000 green channel 8-bit offset dac value (mv) = 250*(dacg[7:0]-127.5)/127.5 r34 (22h) offset dac (blue) 7:0 dacb[7:0] 10000000 blue channel 8-bit offset dac value (mv) = 250*(dacb[7:0]-127.5)/127.5 r35 (23h) offset dac (rgb) 7:0 dacrgb[7:0] - a write to this register location causes the red, green and blue offset dac registers to be overwritten by the new value r36 (24h) pga gain lsb (red) 0 pgar[0] 0 this register bit fo rms the lsb of the red channel pga gain code. pga gain is determined by combining this register bit and the 8 msbs contained in register address 28 hex. WM8224 production data w pd, rev 4.1, june 2012 46 register register name bit no bit name(s) default description r37 (25h) pga gain lsb (green) 0 pgag[0] 0 this register bit fo rms the lsb of the green channel pga gain code. pga gain is determined by combining this register bit and the 8 msbs contained in register address 29 hex. r38 (26h) pga gain lsb (blue) 0 pgab[0] 0 this register bit forms the lsb of the blue channel pga gain code. pga gain is determined by combining this register bit and the 8 msbs contained in register address 2a hex. r39 (27h) pga gain lsb (rgb) 0 pgargb[0] - writing a value to this loca tion causes red, green and blue pga lsb gain values to be overwritten by the new value. r40 (28h) pga gain msbs (red) 7:0 pgar[8:1] 00001100 bits 8 to 1 of red pga gain. combined with red lsb register bit to form complete pga gain code. this determines the gain of the red channel pga according to the equation: red channel pga gain (v/v) = 0.66 + pgar[8:0]x7.34/511 r41 (29h) pga gain msbs (green) 7:0 pgag[8:1] 00001100 bits 8 to 1 of green pga gain. combined with green lsb register bit to form complete pga gain code. this determines the gain of the green channel pga according to the equation: green channel pga gain (v/v) = 0.66 + pgag[8:0]x7.34/511 r42 (2ah) pga gain msbs (blue) 7:0 pgab[8:1] 00001100 bits 8 to 1 of blue pga gain. combined with blue lsb register bit to form complete pga gain code. this determines the gain of the bl ue channel pga according to the equation: blue channel pga gain (v/v) = 0.66 + pgab[8:0]x7.34/511 r43 (2bh) pga gain msbs (rgb) 7:0 pgargb[8:1] - a write to this register location causes the red, green and blue pga msb gain registers to be overwritten by the new value. r44 (2ch) blc control 5 6:0 blc_del [6:0] 0000000 determines the number of pixels (from the start of a line) to delay the start of a blc operation. 7 line_del [8] 0 msb of the number of lines from the start of a frame to delay the start of a blc operation. r45 (2dh) blc control 6 7:0 line_del [7:0] 00000000 lsbs of the number of lines from the start of a frame to delay the start of a blc operation. table 16 register control bits WM8224 production data w pd, rev 4.1, june 2012 47 applications information recommended external components figure 39 external components diagram recommended external component values component reference suggested value description c1 100nf de-coupling for dvdd c2 100nf de-coupling for avdd c3 1 ? f ceramic de-coupling between vrt and vrb (non polarized) c4 100nf de-coupling for vrb c5 100nf de-coupling for vrx c6 100nf de-coupling for vrt c7 100nf de-coupling for vrlc c8 10 ? f reservoir capacitor for dvdd c9 10 ? f reservoir capacitor for avdd table 17 external components descriptions WM8224 production data w pd, rev 4.1, june 2012 48 package dimensions dm101.a fl: 32 pin qfn plastic package 5 x 5 x 0.9 mm body, 0.50 mm lead pitch e2 b b 16 15 8 9 e c 0.08 c ccc a a1 c a3 seating plane 1 l index area (d/2 x e/2) top view d c aaa 2 x c aaa 2 x e 1 17 24 25 32 d2 b c bbb m a 5 4 notes: 1. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from terminal tip. 2. falls within jedec, mo-220, variation vhhd-5. 3. all dimensions are in millimetres. 4. the terminal #1 identifier and terminal numbering convention shall conform to jedec 95-1 spp-002. 5. coplanarity applies to the exposed heat sink slug as well as the terminals. 6. refer to application note wan_0118 for further information regarding pcb footprints and qfn package soldering. 7. this drawing is subject to change without notice. detail 1 a3 g t h w b exposed lead half etch tie bar dimensions (mm) symbols min nom max note a a1 a3 0.80 0.90 1.00 0.05 0.02 0 0.203 ref b d d2 e e2 e l 0.30 0.18 5.00 bsc 3.60 3.45 3.30 0.50 bsc 0.30 0.40 0.50 1 2 2 5.00 bsc 3.60 3.45 3.30 0.10 aaa bbb ccc ref: 0.15 0.10 jedec, mo-220, variation vhhd-5. tolerances of form and position 0.25 h 0.1 0.20 g t 0.103 w 0.15 detail 1 detail 2 detail 2 exposed ground paddle 6 exposed ground paddle bottom view side view 0.30 45 m m WM8224 production data w pd, rev 4.1, june 2012 49 important notice wolfson microelectronics plc (?wol fson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at t he date of shipment. wolfson reserves the right to make changes to its products and s pecifications or to discontinue any produc t or service without notice. customers should therefore obtain the latest version of relevant informati on from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless requi red by law or regulation. in order to minimise risks associated with customer app lications, the customer must use adequate design and operating safeguards to minimise inherent or proc edural hazards. wolfson is not liable fo r applications assistance or customer product design. the customer is solely responsible for its selection and use of wo lfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to re sult in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or pr ocess in which its products or services might be or are used. any prov ision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other not ices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such in formation or for any reliance placed thereon. any representations made, warranties given, and/or liabilities accepted by any person which di ffer from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com WM8224 production data w pd, rev 4.1, june 2012 50 revision history date rev originator changes 15/05/12 4.1 jmacd order codes updated from WM8224sefl and WM8224sefl/r to WM8224csefl and WM8224csefl/r to reflect change to copper wire bonding. 15/05/12 4.1 jmacd package diagram updated to dm101.a |
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